Fabrication of semiconductor integrated circuits (ICs) is an extremely complex process that involves many precise manufacturing and testing operations. Such ICs are fabricated by selectively implanting impurities into, and applying conductive and insulating layers onto, a semiconductor substrate, often called a “wafer.” Semiconductor ICs (or “chips”) are not manufactured individually, but rather as an assembly of typically thousands of IC dies on a wafer, which is then diced to produce the individual IC chips.
Increasing wafer production yield of such dies is an ongoing problem in the manufacture of semiconductor chips. Due to various defects that can occur in the fabrication of a wafer, a significant number of dies are discarded for non-functionality reasons, thereby decreasing the percentage yield per wafer and driving up the cost of the individual chips. Defects are typically caused by foreign particles, minute scratches, and other imperfections introduced during photoresist, photomask, diffusing, or other manufacturing operations. Such wafer yield impacts the number of wafer starts at the inception of production needed to meet specific customer order quantities for finished chips at the end of the production line. With the high demand for semiconductor chips and more orders than can be filled by some production facilities, predicting yield to accurately gauge wafer starts, as well as utilizing defect information to remove yield-detracting operations, are important aspects of improving the efficiency, and hence the output, of the fabrication facility.
In an effort to increase wafer yield, completed IC chips on semiconductor wafers are subjected to a variety of tests to determine which devices function properly so that processing steps can be modified and inoperative devices can be removed from further processing. The testing of a die on a completed wafer, or “multi-probe” testing, is generally performed by coupling logic test signals to the inputs of the dies (via contact pads) and sensing the output signals to determine that the device functions properly. This is referred to as “static” or “DC” testing since low frequency logic input signals are used and the outputs are sensed after the device reaches a steady-state condition. While the static test is important in predicting whether a device will be operable following assembly and packaging, it typically does not insure that a completed device will pass a final test that simulates operation at normal operating frequencies and switching speeds. Thus, “dynamic” or “AC” tests are performed to more accurately predict which die will pass a similar final test after completion. Dynamic testing includes the application of high-speed logic signals to the die while sensing the outputs to measure operating parameters, such as propagation delay times and switching speeds under predetermined load conditions.
Conventional wafer testing techniques typically position a multi-pin probe array in contact with the conductive bond pads on an IC chip. Information from these tests is compared with limits pre-programmed into the test equipment of the test program. The dies are either rejected or accepted based on this comparison. Moreover, this test is typically performed on all the dies on the wafer, often testing dies in one row on the wafer, while simultaneously testing dies in another row, when “multi-site” testing techniques are employed. If a dies fails, the testing program usually instructs a mapping system to mark the particular dies as bad so that it is later discarded when the wafer undergoes singulation (i.e., dicing of the individual dies from one another). Unfortunately, if the testing procedure employed is flawed, otherwise functional chips are erroneously marked as bad and discarded, increasing manufacturing costs. Conversely, if problems are present in the testing procedure, non-functioning or malfunctioning dies may be passed through the process as good dies, typically resulting in inoperative end products. Historically, “correlation wafers” are used to compare the results of the current testing setup, with results from previously tested units.